ABSTRACT
Tools and methodologies for FPGA-based design have been continuously improving over the years in order for them to accommodate the new and extended functionality requirements imposed by increasingly demanding applications. Today’s designs would take unacceptable extremely long times to be completed if tools coming from more than 20 years ago were used. The first important incremental step in accelerating design processes was the replacement of schematic-based design specifications by HDL descriptions (Riesgo et al. 1999).* On one hand, this allows complex circuits (described at different levels of abstraction) to be more efficiently simulated, and on the other hand, designs to be quite efficiently translated (by means of synthesis, mapping, placement, and routing tools) from HDLs into netlists, as a step previous to its translation into the bitstream with which the FPGA is configured (as described in Section 6.2.3.4).
