Complementary metal–oxide–semiconductor (CMOS) transistor scaling over the last 30 years has enabled significant integration of complex electronic circuitry providing improvements in switching speed, density, cost, and functionality of CMOS chips [1]. However, as the thermal voltage kT/q does not scale, the threshold voltage (V T) of CMOS transistors cannot be reduced along with the lithographic dimensions [2]. The threshold voltage of CMOS transistors in the sub-40-nm regime has already been scaled to a value that balances leakage energy and dynamic energy optimally [3]. Further reduction in the threshold voltage would actually increase the amount of energy consumed per operation. Further, there is not much supply voltage scaling expected in smaller technology nodes because of the thermal limit (kT/q) [4,5].