ABSTRACT
The silicon nanowire field-effect transistor (NWFET) has been extensively studied because of its potential for further scaling down of the complementary metal-oxide semiconductor (CMOS) technology. In particular, it has been reported that the NWFET with gate-all-around (GAA) structure shows excellent gate controllability by which low leakage current and effective suppression in a short channel effect are guaranteed [1–5]. Furthermore, as an effective channel length (L EFF) and channel diameter (d NW) shrink down to a sub-20 nm regime, the quantum confinement effect in volume-channel inversion and less surface scattering of carriers in such a short nanowire channel enables the NWFET to operate in a quasi-ballistic transport regime [6–8]. Owing to this enhanced electrostatic nature, the NWFET is expected to exhibit superb electrical characteristics, including large current drivability and high mobility, some of which have already been observed [1–5,9]. The NWFET, however, in spite of its numerous advantages, has a few technical issues such as parasitic resistance and capacitance components due to the structural particularity [10–12]. It is thus 738required to exactly extract such parasitic components to exactly estimate the electrical properties and optimize the structure of the NWFET, providing feedback to the fabrication process.
