Recently, nanowires (NWs) have come into the spotlight for future integrated optoelectronic devices. III–V compound semiconductor NWs are unique, in that they can be grown epitaxially on Si substrates, which allow the integration of III–V-based optoelectronics with established Si microelectronics technologies [1–3]. That is to say, well-aligned NW morphology with vertical growth is a rudimentary necessity in the applications of III–V compound semiconductor NWs on Si substrates. However, several problems must be overcome to obtain the successful integration of III–V compound semiconductors with Si [4,5], including lattice and thermal expansion mismatch, and the formation of antiphase domains. For the case of Si, in particular, the existence of a native oxide layer at the interface between NWs and substrates is a major factor preventing the epitaxial growth of NWs [1]. To achieve nanoscale optoelectronic devices, it is also crucial to fabricate NWs with a high-quality crystal structure and controllable composition. For optoelectronic device applications, NW defects such as twin defects, phase polytypism, and stacking faults may give rise to the deterioration of optical and carrier transport properties and are therefore undesirable [6]. Overcoming these issues, namely, the interface defects between NWs and substrates and crystal 604structure defects, is the first priority to obtain perfect III–V compound semiconductor NWs on Si substrates for nanoelectronic device applications.