Silicon device technology scaling and performance improvement require [1–3] not only overcoming a variety of fabrication challenges but also suppressing systematic variation and random effects [4–7]. Except process variation effect (PVE), random dopant fluctuation (RDF), as one of the known major intrinsic parameter fluctuations, complicates device manufacturing and degrades device characteristics in the nanometer scale complementary metal–oxide semiconductor (nano-CMOS) device era [8–30]. High-κ/metal-gate (HKMG) technology has been a key way to suppress RDF-induced variability and reduce leakage current [31–38]; however, HKMG may introduce random interface traps (ITs) at a high-κ/silicon interface and such IT fluctuation (ITF) degrades device characteristics considerably [39–47]. Various simulations of the device’s variability induced by ITF were reported by using a one-dimensional (1D) IT’s model for sub-65-nm CMOS devices [46], a 2D IT’s model for 16-nm-gate HKMG devices [39], local interaction of the combined RDs and ITs [40,41], and full fluctuation among all random sources [4]. Recently, the asymmetric RDF on device characteristics was studied for 16-nm-gate HKMG metal–oxide–semiconductor field effect transistor (MOSFET) devices [48,49]. However, induced by random ITs, asymmetric physical and electrical characteristic fluctuations of 16-nm-gate HKMG MOSFETs have not been discussed yet.