ABSTRACT
Resistive switches [1] are two-terminal devices that offer a nonvolatile switching behavior when applying voltage pulses. Although individual devices have a low-power requirement [2], passive crossbar arrays show significant power losses due to parasitic current sneak paths [3]. This so-called “sneak-path problem” does not only lead to increased power consumption, but it also complicates or even prevents proper array read operations. In Figure 23.1, a section of a passive crossbar array is depicted, illustrating the read operation of the lower left element. In case 1, the element is considered to be in the high-resistive state (HRS), while in case 2 the element is considered to be in the 316low-resistive state (LRS). Since neighboring cells are low resistive in both cases, the read currents are large in both cases, making a proper reading difficult. To solve this problem, the implementation of a rectifying diode-like selection device was suggested so far [4]. However, this approach is difficult to realize for bipolar resistive switches, since high current densities are required. In an alternative approach, antiserially connected bipolar resistive switches are applied to form a complementary resistive switch (CRS) [5,6]. Complementary resistive switches alleviate size limitations for passive crossbar array memory devices by the elimination of sneak paths because of high-resistive storing states. In Figure 23.2, the basic behavior of a CRS cell is illustrated. If, for example, element B is in the LRS and element A is in the HRS, almost all voltage drops at element A until V th,1 is reached. At this point (A), element A switches to the LRS and element B remains in the LRS, because the potential drop at A is far below V th,RESET. The CRS state is defined as “ON” with both elements how being low resistive and having an equal voltage drop. If the voltage reaches V th,2(B), element B becomes high resistive, because this is equivalent to a voltage drop of V th,RESET at element B. This state is defined as “0.” For all applied voltages larger than V th,3, element B stays high resistive and element A low resistive. If a potential V comes into the range V th,4 < V < V th,3(C), the high-resistive element B switches to the LRS and both elements in the CRS are in the LRS (state “ON”). If the negative potential exceeds V th,4, element A switches back to HRS (D) and the resulting state is “1.” In Table 23.1, the CRS states are depicted. The “OFF” state is only found in uninitialized cells and is not considered further in the following. The states “0” and “1” are the logical storage states and the state “ON” occurs only on a reading of the memory state. The internal memory states “0” and “1” of a CRS cell are indistinguishable at low voltages because state “0” as well as state “1” show a high resistance. Therefore, no parasitic current paths, which can only be induced by low-resistive cells in the crossbar, can arise. To read the stored information (“0” or “1”) of a single CRS cell, a read voltage must be applied to the CRS cell. If the CRS cell is in state “1,” the cell switches to the “ON,” state and if the cell is in state “0,” the cell remains in state “0.” By this selective switching 317to the “ON,” state, the stored information is destroyed (destructive read). An alternative destructive read approach uses a voltage V > V th,2 resulting in a current spike when HRS/LRS applies while no current spike occurs for LRS/HRS. In ref. [7], this mode is used for logic applications. Note that for a destructive readout, it is necessary to write back the previous state of the cell after the reading. This requirement is not present when using a nondestructive readout scheme as proposed in ref. [8]. In general, the writing of state “1” requires a negative voltage (V < V th, 4), and for writing a “0” a positive voltage V > V th, 2 is required. CRS States
CRS
Element A
Element B
Overall Resistance
0
HRS
LRS
≈ HRS
1
LRS
HRS
≈ HRS
ON
LRS
LRS
LRS + LRS
OFF
HRS
HRS
>> HRS; only initial state
Sneak-path problem in passive crossbar arrays. https://s3-euw1-ap-pe-df-pch-content-public-u.s3.eu-west-1.amazonaws.com/9781315216089/1a39fa69-e426-4ca1-a1b7-b7d35c28e418/content/fig23_1.tif"/> A complementary resistive switch results from the antiserial connection of two elements A and B. For example, M1 is Cu and M2 is Pt. https://s3-euw1-ap-pe-df-pch-content-public-u.s3.eu-west-1.amazonaws.com/9781315216089/1a39fa69-e426-4ca1-a1b7-b7d35c28e418/content/fig23_2.tif"/>