ABSTRACT
The latest ITRS (International Technology Roadmap for Semiconductors) [1] has identified power consumption as a grand challenge for nanoelectronics. A related daunting task is represented by the passive wires (interconnects), see [2–8]. They are the ones driving the power/energy consumption, as their number increases exponentially (each device has to be connected by several wires to other devices, and the number of devices is following the exponential Moore’s law), while their scaling is limited (as their parasitic capacitances and RC-delays are not scaling in sync with the devices). In fact, the huge processing potential offered by parallel architectures will not be realized satisfactorily without addressing the interconnection challenge which is intimately entangled with power and energy consumption. During the 2011 International Solid-State Circuits Conference, power consumption has been a leitmotif [9]. Dr. Oh-Hyun Kwon, the president of Samsung Electronics, has stated the need “to reduce power consumption by a compound annual rate of 20% over the next decade,” while Professor Asad Abidi (University of California, Los Angeles) has mentioned that the power efficiency challenge “requires radical changes in the way we do things.” One of the radical approaches—advocated by Dr. Jack Sun, Vice President for Research and Development and Chief Technology Officer of TSMC, to solve the challenges associated with power constraints—the chip industry could envisage is to “get some inspiration from the amazing human brain.” On the one hand, structures in the brain are characterized by massive interconnections, but, contrary to common thought, most of these are local with an amazingly sparse global interconnect network. On the other hand, cortical neurons possess an average of 8000 (up to a maximum of 100,000) synaptic connections, which differentiate them significantly from present-day CMOS (complementary metal–oxide–semiconductor) gates having an average of four inputs only. With on the order of 1010 neurons in the human cortex, and about 1014 synaptic connections, the brain is inspirational for the future of interconnects (supporting massively parallel multi-/many-cores) due to its ultra-low-power consumption (about 20 W) and extreme reliability. This is because the neurons themselves are able to communicate (dendritic and axonal communications) at quite large distances on a very limited power budget.
