ABSTRACT
Prevailing synchronous digital ICs use clocks to synchronize and coordinate the operations of circuit components. While the clocked control mechanism is efficient and simplifies circuit design, it also limits the flexibility and reliability of synchronous circuits. Any violations in setup time or hold time will cause the circuit to malfunction. Therefore, timing analysis and closure are critical in synchronous digital circuit design. Extreme temperature environments pose significant challenges to semiconductor ICs. Under extreme temperature, the drastic changes in device mobility induce corresponding variations in transistor switching speed, which in turn affect each circuit component. Such large speed variations are very likely to cause timing violations in synchronous circuits. A possible solution is to perform timing analysis at every temperature point, and leave sufficient margins in clock frequency to accommodate speed changes. However, this will significantly degrade performance since the circuit will always operate at the worst-case scenario. A digital circuit design paradigm, which is robust, low overhead, and capable of operating automatically over large temperature swings, is in desperate need for extreme temperature applications.
