ABSTRACT
It has been shown in IBM technology qualifications that the reliability for FET devices in SiGe integrated technologies is comparable to that of the base CMOS technology for the major reliability mechanisms of hot carrier, gate dielectric, and negative bias temperature instability (NBTI). The reliability models generated for the base technologies will adequately predict integrated SiGe parameter shifts and estimated lifetimes. In this chapter, we will present some additional CMOS reliability considerations and methodologies that can be applied under extreme operating environments for the “gradual” shift CMOS mechanisms (hot carrier and bias temperature instability [BTI]).
