ABSTRACT
The goal of achieving terahertz (THz) speeds using silicon-based transistors has generated significant recent interest. In this chapter, we use operating temperature to explore the performance limits of SiGe HBTs. Different approaches for vertical profile scaling and parasitics reductions are investigated. Record peak f T (current-gain cutoff frequency), f max (maximum oscillation frequency), f T × BVCEO (open-base collector–emitter breakdown voltage), and τgate (ring oscillator gate delay) were achieved at cryogenic temperatures using modest lithography. These remarkable levels of performance demonstrate the capabilities of a silicon-based transistor reaching half-THz frequency response. The consequences of cooling SiGe HBTs are in many ways similar to that of combined vertical and lateral device scaling. The associated device physics observed at cryogenic temperatures in these devices provide important insights into further device scaling for THz speeds at room temperature. A new scaling roadmap predicts that f T and f max of room-temperature SiGe HBTs could potentially achieve 800 and 900 GHz with a BVCEO of 1.1 V at 32 nm lithography node. The experimental work and some discussions presented in this chapter can also be found in Refs. [1–7].
