ABSTRACT
In the late 1970s, NMOS transistors (n-channel MOSFETs on p-substrate) were the key building blocks in MOS technology. However, since the late 1980s, complementary MOS (CMOS) have become fashionable. For more than 20 years now, CMOS has been the faithful workhorse. The package density of transistors increased over the years, because the MOS transistors (see figure 5.1.1) could easily be scaled down in size without a performance penalty. The key feature of CMOS (see figure 5.1.2) is the ability to limit power dissipation. With the CMOS inverter structure, power is only consumed during switching operations. In between switching operations, power dissipation is limited to source to drain leakage current in the off state (off-state leakage). Until recent times, leakage current through the gate (gate leakage) could be neglected. However, with gate thickness shrinking to a point where direct tunnelling current through the gate becomes large, gate leakage should be taken into account too. Generally speaking, gate leakage becomes a problem when gate leakage ≥ off current. Though this depends on the transistor design for a specific application area (see below), generally speaking, gate leakage becomes a concern when it exceeds 1 – 10 A cm−2. This will happen when the equivalent oxide thickness (EOT) drops below 1.5 and approaches 1.0 nm around 2006 [1]. Schematic representation of a MOS transistor. https://s3-euw1-ap-pe-df-pch-content-public-u.s3.eu-west-1.amazonaws.com/9780429092886/2b9b87e7-7721-40bf-9e76-98890f6459e8/content/fig5_1_1.jpg"/> Schematic representation of a CMOS building block. https://s3-euw1-ap-pe-df-pch-content-public-u.s3.eu-west-1.amazonaws.com/9780429092886/2b9b87e7-7721-40bf-9e76-98890f6459e8/content/fig5_1_2.jpg"/>
