ABSTRACT
In most digital signal processing (DSP) systems, one of the key hardware block is a multiplier. In a typical DSP applications, a multiplier plays an important role that includes digital communications, digital filtering, and spectral analysis. Many present that DSP applications are targeted at portable, battery-operated systems so that one of the primary design constraint is a power dissipation. In the design field, there are many multipliers available to increase the performance level. In this chapter, approximate compressors used in a parallel multiplier are proposed. The two new approximate 4-2 compressors propose that the simplified compressors have better power consumption than the optimized 4-2 compressor existing designs. The renovation module of a parallel multipliers are going to use these approximate compressors. For a parallel multiplier, four different outlines exploiting the proposed approximate compressors are proposed and analyzed. The design of multiplier relies on the compressor and can meet with the respect to the circuit-based design. The results of the proposed design show and accomplish substantial declines in delay, transistor count, and power dissipation compared to an exact compressor design; likewise, two of the future multiplier designs offer an brilliant proficiencies for multiplication of an image.
