The goal of the test process for integrated circuits is to separate good devices from bad devices, and to test good devices as good. Bad devices tested as bad become yield loss, but they also represent opportunity for cost reduction as we reduce number of defects in the process. When good devices are tested as bad, overkill occurs and this directly impacts cost and profits. Finally, bad devices tested as good signal a quality problem, usually represented as defects per million (DPM) devices delivered.