Three-dimensional integrated circuit (3D IC) is a promising technology that has potential to achieve higher device densities than technology scaling alone while improving energy efficiency. 3D ICs utilize vertical dimension for stacking different ICs. The vertical stacking largely reduces the total wire length and routing congestion compared to a conventional 2D implementation, and thus reduces interconnect delay and power consumption [1, 2]. Furthermore, 3D IC technology can broaden the horizon of what a system-on-chip can achieve by providing the capability to integrate disparate integrated technologies (such as technologies supporting radio frequency (RF) and high-performance logic devices) on a single chip. This type of heterogenous technology integration can significantly reduce the delay and power consumption [3, 4], and thus facilitates building energy-efficient systems. Moreover, even within one technology, different generations (for example, 45 and 32 nm logic CMOS) can be stacked to realize the cost-benefit from the better yield of the mature node [5].