Traditional silicon-based CMOS field-effecttransistors (FETs) cannot satisfy the requirements of future high-speed low-power integrated circuits due to their ultra–high-power consumption at deep-nanometer regime. Moreover, conventional FETs cannot overcome the subthreshold swing (SS) limit of 60mV/decade. Negative capacitance field-effect transistors (NC-FETs) are considered as one of the most promising transistor technologies for future high-speed and low–power-integrated circuits due to their unique features, such as high ON current (ION ), low OFF current (IOFF ), SS limit of sub-60 mV/decade, low-threshold voltage (Vth ), ultra–low-power consumption, and high-switching current ratio (ION /IOFF ). NC-FETs can be realized using ferroelectric materials. By varying the ferroelectric properties, the DC and RF characteristics of the transistor can be tuned to the desirable level. This chapter deals with the various architectures of NC-FETs, performance-enhancement techniques of NC-FETs, scalability of NC-FETs, ferroelectric materials for NC-FETs, FSOI-NC-FETs, 2-dimentional NC-FETs, analog/RF performance of NC-FETs, DC characteristics of NC-FETs, effect of traps 318on the performance of NC-FETs, work-function engineering in NC-FETs, negative capacitance carbon nanotube FETs, impact of gate-stack structure on NC-FET performance, NC-FinFET, switching-speed limitation of NC-FETs, gate-stress engineering in NC-FETs, impact of temperature on NC-FET performance, and modeling of drain current in NC-FETs.