To maintain a proper control of the drain current flow in nanoscale CMOS devices, the thickness of silicon dioxide which has been used as the gate dielectric material for over four decades is now pushed into its technological limit of about 1 nm and theoretical limit of 0.7 nm. Further device downsizing would require even thinner gate dielectric films. This stringent requirement can only be achieved by using a high-dielectric constant (high-k) material. High-k gate dielectric together with metal gate electrode has been recognized as an effective technological option to boost the performance of present integrated circuit technology However, there are still a lot of issues need to be solved in 106order to incorporate this new material into the existing CMOS technology. This chapter reviews the development of high-k gate dielectric materials for nanoscale CMOS device applications. We shall focus on the issues related to the electrical properties and the reliability of high-k materials used as the MOS gate dielectrics.